Subrat Panda, PhD

Sahibzada Ajit Singh Nagar, Punjab, India
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Steering AGNEXT's technological helm, my role weaves AI and IoT to revolutionize…

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Experience & Education

  • Manifest AI

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Licenses & Certifications

Volunteer Experience

  • IEEE Graphic

    Student Volunteer

    IEEE

    - 2 years

    Science and Technology

    I was the IEEE student body chair person for 2 years.

  • Volunteer and Chief Coordiantor

    IIT Technology Alumni Association, Bangalore

    - Present 11 years 2 months

    Science and Technology

    Alumni Association Activities in Bangalore.

  • IIT Kharagpur Alumni Bangalore Chapter Graphic

    Executive Council Member

    IIT Kharagpur Alumni Bangalore Chapter

    - 2 years

    Science and Technology

  • Governing Council Member

    IIT Alumni Center, Bangalore

    - Present 6 years

    Science and Technology

Publications

  • System and Method to validate branches in a processor with or without a reference model

    www.ip.com

    IPCOM000232662D

    Generating testcases consisting of branch instruction with reference model is difficult problem. This is because maintaining the branch taken and not taken path through out the test generation becomes complex as the number of conditional branches increases. Another problem with the above approach is that the testcases progress only through the specified path at the time of testcase generation. We propose a solution where, a normal reference model based testcase without…

    IPCOM000232662D

    Generating testcases consisting of branch instruction with reference model is difficult problem. This is because maintaining the branch taken and not taken path through out the test generation becomes complex as the number of conditional branches increases. Another problem with the above approach is that the testcases progress only through the specified path at the time of testcase generation. We propose a solution where, a normal reference model based testcase without branches can be integrated with branches, while maintaining the dataflow of the original testcase. This ensures that the final testcase with branches is compatible with the reference model based test generation. Our solution is capable of of generating branches dynamically, that is, any testcase can be modified to have a different set of branches for each run.

    Other authors
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  • Method for efficient regression of floating point on accelerated simulation

    www.ip.com

    The features described is an acceleration (or emulation) specific solution which enables a fast regression of the FP unit, but "compressing" a large set of FP test-cases into a self-executing, self-checking, program. This can be used, for example, to get basic confidence in the FPU implementation prior to (or in parallel to) putting it into the more extensive (but much slower) simulation.

    Other authors
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  • Leveraging Accelerated Simulation for Floating-Point Regression

    Springer's Lecture Notes in Computer Science series (LNCS)

    Accelerated simulation (acceleration) platforms play a pivotal role in the verification of today’s complex designs. Currently, acceleration is used with either adapted pre-silicon tools or post-silicon tools. We present a novel acceleration-only tool, which enables a fast and efficientmethodology for floatingpoint regression. We overcome the lack of test-bench in this environment through self-checking.

    Other authors
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  • Assertion-Based Verification of Mixed-Signal Behaviors with Sampling Clock

    Synopsys User Group Conference, India

    Other authors
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  • A Formal Approach for Specification Driven AMS Behavioral Model Generation

    Proceedings of the Conference on Design, Automation and Test in Europe

    Other authors
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  • Mode Based Functional Partitioning of Design Intent for BehavioralModeling of Large AMS Circuits

    VLSI Design and Test Symposium

    In this paper we propose a mode based functional partitioning methodology for developing behavioral models (BM) of large analog and mixed signal (AMS) circuits. We divide the state-space of an AMS circuit into several exclusive modes of operation, based on its functionality and then model each of the modes either from specification and/or from transistor level netlist. The models thus developed have a modular architecture and enables convenient reuse of the BMs in future designs. The method…

    In this paper we propose a mode based functional partitioning methodology for developing behavioral models (BM) of large analog and mixed signal (AMS) circuits. We divide the state-space of an AMS circuit into several exclusive modes of operation, based on its functionality and then model each of the modes either from specification and/or from transistor level netlist. The models thus developed have a modular architecture and enables convenient reuse of the BMs in future designs. The method also provides users with flexibility of modeling different modes at different detailing. The models are represented in Verilog-A and can exhibit significant speedup, depending on the detailing used to model each mode. Two most pertinent applications of these models are in (i) system level verification and (ii) testbench development.

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Patents

  • EFFICIENT DEBUGGING OF MEMORY MISCOMPARE FAILURES IN POST-SILICON VALIDATION

    Issued US 20150186227

    Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is as follows: (i) receiving a first memory location that is subject to a miscompare between an associated simulation value for the first memory location and an associated actual value for the first memory location; (ii) backtracking through instructions of a test case to determine the identity of a set of backtrack locations upon which the…

    Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is as follows: (i) receiving a first memory location that is subject to a miscompare between an associated simulation value for the first memory location and an associated actual value for the first memory location; (ii) backtracking through instructions of a test case to determine the identity of a set of backtrack locations upon which the first memory location is dependent, with the set of backtrack locations being made up of at least one of: memory locations and register locations; and (iii) comparing respective simulation values and actual values for at least one of the backtrack locations to help determine a cause of the miscompare at the first memory location.

    Other inventors
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  • DETECTING MISSING WRITE TO CACHE/MEMORY OPERATIONS

    Issued US 20150170764

    Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write…

    Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.

    Other inventors
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  • Chip stack cache extension with coherency

    Issued US 20150106569

    By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.

    Other inventors
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  • Software-hardware adder

    Issued US US 8825727 B2

    A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is…

    A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index.

    Filed on : Mar 15, 2012, Granted Sep 02, 2014.

    Other inventors
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Courses

  • Compilers

    -

  • Operating Systems

    -

Honors & Awards

  • Freedom of the Hall, Azad hall of Residence

    Azad Hall of Residence

    It was awarded for service to the Hall of my stay in my second year of education at IIT Kharagpur.

Languages

  • English

    Full professional proficiency

  • Hindi

    Professional working proficiency

  • Oriya

    Limited working proficiency

  • Bengali

    Limited working proficiency

Organizations

  • IEEE Computer Society, Bangalore Section

    Chairperson

    -

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