San Francisco, California, United States
10K followers 500+ connections

Join to view profile

About

I scaled Outlook Mobile from 0 to 60 million monthly active users at Microsoft.

I…

Articles by James

See all articles

Activity

Join now to see all activity

Experience & Education

  • Bryj Technologies, Inc.

View James’s full experience

See their title, tenure and more.

or

By clicking Continue to join or sign in, you agree to LinkedIn’s User Agreement, Privacy Policy, and Cookie Policy.

Licenses & Certifications

Volunteer Experience

  • Founder

    Highground Hackers

    - 1 year 4 months

    Social Services

    A group of civic minded developers and entrepreneurs working to connect engineering talent with non-technical experts in different fields of public concern. Organized multiple hackathons and developer weekends that resulted in applications being deployed for organizations such as Cure Violence, one of the top 50 NGO's in the world.

Patents

  • Integrated circuit with multiple functions sharing multiple internal signal buses according to distributed bus access and control arbitration.

    Issued US 5,774,684

    An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses…

    An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently. The IC may provided with a processor core with features that support In-Circuit Emulation (ICE).

    Other inventors
    • Ralph Haines
    See patent

  • Bidirectional parallel data port having multiple data transfer rates, master, and slave operation modes, and selective data transfer termination

    Issued US 5,710,939

    A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and…

    A bidirectional parallel signal interface for providing a parallel data interface between a computer and an external peripheral device includes an interface circuit with command registers for communicating commands and data, a first-in, first-out (FIFO) memory for communicating data between the computer and the peripheral device, and host and slave state machines for receiving commands from the command registers and in accordance therewith controlling communication of data between the FIFO and peripheral device and communicating control signals to and from the peripheral device. The communication of data between the FIFO and peripheral device is effected in accordance with data communication rates which are controlled by the host and slave state machines in accordance with the commands from the command registers. The communications of control signals by the host and slave state machines are responsive to their control signals with such responsiveness being controllable in accordance with the commands from the command registers. The communication of data from the FIFO to the peripheral device is halted by the host state machine in accordance with its commands from the command registers. The command registers include a status register for storing data from the peripheral device representing a number of status states of the peripheral device.

    Other inventors
    • william ballachino
    • franco Iacobelli
    See patent

Honors & Awards

  • LECTURES & PRESENTATIONS

    -

    ► Keynote Speaker at Product Management & Innovation 2018
    ► Speaker and Panelist at Microsoft Ignite 2017
    ► Keynote Speaker at Velocity 2014: “Building Self-Adaptive Autonomous Infrastructure”
    ► Social Media Marketing Instructor for 2010 semester at UC Santa Cruz, CA

Languages

  • Japanese

    Professional working proficiency

  • English

    Native or bilingual proficiency

  • French

    Limited working proficiency

Recommendations received

18 people have recommended James

Join now to view

More activity by James

View James’ full profile

  • See who you know in common
  • Get introduced
  • Contact James directly
Join to view full profile

Other similar profiles

Explore more posts

Explore top content on LinkedIn

Find curated posts and insights for relevant topics all in one place.

View top content

Others named James Colgan

116 others named James Colgan are on LinkedIn

See others named James Colgan

Add new skills with these courses

See all courses